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copyright ? cirrus logic, inc. 1998 (all rights reserved) cs4622/24 preliminary product bulletin crystalclear? soundfusion? pci audio accelerator features n 300/255 mips slimd ? dsp architecture n directx ? 5.0 3d positional audio n fat labs approved 64-voice wavetable synthesis with effects n netmeeting ? aec hardware acceleration n dolby ? digital ac-3 ? (cs4622) n high quality hardware sample rate conversion (90+ db dynamic range) n pc/pci legacy support n ddma legacy support n crystalclear legacy support (ccls ? ) n pci 2.1 compliant pci interface n 96 stream dma interface with hardware scat- ter/gather support n pci power management (d0 through d3 hot), apm 1.2, and acpi 1.0 support n ac 97 2.0 link codec interface n secondary ac 97 1.0/2.0 link codec interface for multi-channel and digital docking support n asynchronous digital serial interface (zv port) n s/pdif digital input and output interfaces sup- porting both pcm and dolby digital 5.1 formats n mpu-401 midi input/output interface n 3.3 v power supply (5 v tolerant i/o) description the cs4622/24 is a high performance pin-compat- ible upgrade to the 128-pin cs4610c pci audio accelerator. with the added legacy compatibility modes, the cs4622/24 enables real mode dos compatible pci-only audio subsystems. this de- vice, combined with application and driver software, provides a complete system solution for hardware acceleration of windows 95 ? direct- sound ? , directsound3d ? , directinput, and wavetable synthesis. wdm drivers provide sup- port for both windows 98 and windows nt 5.0. the cs4622/24 is based on the cirrus logic crys- talclear stream processor (sp) dsp core. the sp core is optimized for digital audio processing, and is powerful enough to handle complex signal pro- cessing tasks such as dolby digital ac-3 decoding (cs4622 only) with ease. the sp core is support- ed by a bus mastering pci interface and a built-in dedicated dma engine with hardware scatter- gather support. these support functions ensure extremely efficient transfer of audio data streams to and from host-based memory buffers, providing a system solution with maximum performance and minimal host cpu loading. the all-digital cs4622/24 supports a variety of au- dio i/o configurations including direct connection to the crystalclear cs4297 ac 97 codec. a sec- ondary ac 97 2.0 interface provides support for multi-channel and digital docking solutions. added extended i/o supports daa control for modem applications. consumer digital input and output (s/pdif) inter- faces support both pcm and compressed 5.1 digital data formats. pc/pci, ddma, and crystalclear legacy support provide pci-only legacy games compatibility. ordering information cs4622-cq 128-pin tqfp 20x14x1.60 mm CS4624-cq 128-pin tqfp 20x14x1.60 mm ds293pp2 june 98 cirrus logic preliminary product bulletin june 30, 4:24 pm
2 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator absolute maximum ratings (pcignd = cgnd = crygnd = 0 v, all voltages with respect to 0 v) notes: 1. includes all power generated by ac and/or dc output loading. 2. the power supply pins are at recommended maximum values. xtali & xtalo are at 3.6 v maximum. 3. at ambient temperatures above 70 c, total power dissipation must be limited to less than 0.4 watts. warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (pcignd = cgnd = crygnd = 0 v, all voltages with respect to 0 v) specifications are subject to change without notice. parameter symbol min typ max unit power supplies pcivdd cvdd cryvdd vdd5ref - - - - - - - - 4.6 4.6 4.6 5.5 v v v v total power dissipation (note 1) - - 1.5 w input current per pin, dc (except supply pins) - - 10 ma output current per pin, dc - - 10 ma input voltage (note 2) -0.3 - 5.75 v ambient temperature (power applied) (note 3) -45 - 85 c storage temperature -55 - 150 c parameter symbol min typ max unit power supplies pcivdd cvdd cryvdd vdd5ref 3 3 3 4.75 3.3 3.3 3.3 5 3.6 3.6 3.6 5.25 v v v v internal dsp frequency - - 85 mhz operating ambient temperature t a 02570c dolbys ac-3 technology is implemented on the cs4622 stream processor only. supply of this implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use this implementation in any finished end-user or ready-to-use final product. it is hereby notified that a license for such use is required from dolby laboratories. dolby and ac-3 are registered trademarks of dolby laboratories licensing corporation. windows, windows 95, directsound, and directsound3d are registered trademarks of microsoft corporation. directinput, directx and netmeeting are trademarks of microsoft corporation. sound blaster and sound blaster pro are trademarks of creative technology, ltd. crystal, crystalclear, ccls, slimd and soundfusion are trademarks of cirrus logic, inc. all other names are trademarks, registered trademarks, or service marks of their respective companies.
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 3 cs4622/24 crystalclear? soundfusion? pci audio accelerator ac characteristics (pci signal pins only) (t a = 70 c; pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; reference levels = 1.4 v; unless otherwise noted; (note 4)) notes: 4. specifications guaranteed by characterization and not production testing. 5. refer to v/i curves in figure 1. specification does not apply to pciclk and rst# signals. switching current high specification does not apply to serr#, pme#, and inta# which are open drain outputs. 6. cumulative edge rate across specified range. rise slew rates do not apply to open drain outputs. 7. equation a: i oh = 11.9 * (vout - 5.25) * (vout + 2.45) for 3.3 v > vout > 3.1 v 8. equation b: i ol = 78.5 * vout * (4.4 - vout) for 0 v < vout < 0.71 v parameter symbol min max unit switching current high (note 5) 0 < vout < 1.4 1.4 < vout < 2.4 3.1 < vout < 3.3 i oh -44 - - - note 7 ma ma switching current low (note 5) vout > 2.2 2.2 > vout > 0.55 0.71 > vout > 0 i ol 95 vout/0.023 - - - note 8 ma ma low clamp current -5 < vin < -1 i cl -ma output rise slew rate 0.4 v - 2.4 v load (note 6) slewr 1 5 v/ns output fall slew rate 2.4 v - 0.4 v load (note 6) slewf 1 5 v/ns 44 C vout 1.4 C 0.024 --------------------------- + 25 C vin 1 + 0.015 ------------------ - + pull up pull down equation b: equation a: 3.3 3.3 2.2 0.55 2.4 voltage voltage 1.4 dc drive point dc drive point ac drive point i = 11.9*(vout-5.25)*(vout+2.45) for 3.3v > vout > 3.1v oh i = 78.5*vout*(4.4-vout) for 0v < vout < 0.71v ol ac drive point test point test point -2 3, 6 95 380 - 44 current (ma) current (ma) - 176 figure 1. ac characteristics
4 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator dc characteristics (t a = 70 c; pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; all voltages with respect to 0 v unless otherwise noted) notes: 9. the following signals are tested to 6 ma: frame#, trdy#, irdy#, devsel#, stop#, serr#, perr#, and inta#. all other pci interface signals are tested to 3 ma. 10. input leakage currents include hi-z output leakage for all bi-directional buffers with three-state outputs. 11. for open drain pins, high level output voltage is dependent on external pull-up used and number of attached gates. 12. typical values are given as average current with typical sp task execution and data streaming. current values vary dramatically based on the software running on the sp. parameter symbol min typ max unit pci interface signal pins high level input voltage v ih 2-5.75v low level input voltage v il -0.5 - 0.8 v high level output voltage iout = -2 ma v oh 2.4 - - v low level output voltage iout = 3 ma, 6 ma (note 9) v ol --0.55v high level leakage current vin = 2.7 v (note 10) i ih --70a low level leakage current vin = 0.5 v(note 10) i il ---70a non-pci interface signal pins (except xtalo) high level input voltage xtali other pins v ih 2.3 2 3.3 - 4.0 5.75 v v low level input voltage xtali other pins v il -0.5 -0.5 0 - 0.8 0.8 v v high level output voltage iout = -4 ma (note 11) v oh 2.4 - - v low level output voltage iout = 4 ma v ol --0.4v high level leakage current vin = 5.25 v i ih --10a low level leakage current vin = 0 i il ---10a parameter min typ max unit power supply pins (outputs unloaded) power supply current: vdd5ref pcivdd/cvdd/cryvdd total (notes 4,12) - - 0.6 164 - tbd ma ma low power mode supply current - 10 - ma
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 5 cs4622/24 crystalclear? soundfusion? pci audio accelerator pci interface pins (t a = 0 to 70 c; pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v) notes: 13. for active/float measurements, the hi-z or off state is when the total current delivered is less than or equal to the leakage current. specification is guaranteed by design, not production tested. 14. rst# is asserted and de-asserted asynchronously with respect to pciclk. 15. all output drivers are asynchronously floated when rst# is active. parameter symbol min max unit pciclk cycle time t cyc 30 - ns pciclk high time t high 11 - ns pciclk low time t low 11 - ns pciclk to signal valid delay - bused signals t val 211ns pciclk to signal valid delay - point to point t val(p+p) 212ns float to active delay (note 13) t on 2-ns active to float delay (note 13) t off -28ns input set up time to pciclk - bused signals t su 7-ns input set up time to pciclk - point to point t su(p+p) 10, 12 - ns input hold time for pciclk t h 0-ns reset active time after pciclk stable (note 14) t rst-clk 100 - m s reset active to output float delay (notes 13, 14, 15) t rst-off -40ns pciclk t rst-clk rst# outputs hi-z inputs valid input t on t off t su t h outputs valid t val t rst-off figure 2. pci timing measurement conditions
6 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator ac 97 serial interface timing (t a = 0 to 70 c; pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v; unless otherwise noted) zv port timing parameter symbol min typ max unit abitclk/abitclk2 cycle time t aclk 78 81.4 - ns abitclk/abitclk2 rising to asdout/adsout2 valid t pd5 -1725ns asdin/asdin2 valid to abitclk/abitclk2 falling t s5 15 - - ns asdin/asdin2 hold after abitclk/abitclk2 falling t h5 5--ns pciclk rising to arst#/arst2# valid t pd6 -10- ns parameter symbol min max unit zlrck delay after zsclk rising t slrd 2-ns zlrck setup before zsclk rising t slrs 32 - ns zsclk low period t sclk 22 - ns zsclk high period t sclkh 22 - ns zsdata setup to zsclk rising t sdlrs 32 - ns zsdata hold after zsclk rising t sdh 2-ns pciclk t aclk pd5 h5 pd6 t t t t s5 figure 3. ac 97 configuration timing diagram abitclk/abitclk2 async/async2 asdout/asdout2 asdin/asdin2 arst#/arst2# sclkh t slrs t slrd t sdlrs t sdh t sclkl t zsdata zsclk zlrck figure 4. zv port
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 7 cs4622/24 crystalclear? soundfusion? pci audio accelerator independent timing environment (t a = 0 to 70 c; pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0v, logic 1 = 3.3 v; timing reference levels = 1.4 v; xtali = 12.288 mhz; unless otherwise noted) parameter symbol min typ max units sclk output cycle time t sclk 312 326 - ns fsync output cycle time (@sclk falling edge) t fsync 20000 20833 - ns sclk falling to fsync transition t pd7 -45 2 45 ns lrclk output cycle time (@ sclk rising edge) t lrclk 20000 20833 - ns sclk rising to lrclk transition t pd8 -45 2 45 ns sclk falling to sdout/sdo2/sdo3 valid t pd9 -245ns sdin/sdin2 valid to sclk rising (si1f2-0: 010, si2f1-0: 00) t s6 30 - - ns sdin/sdin2 hold after sclk rising (si1f2-0: 010, si2f1-0: 00) t h6 30 - - ns sdin/sdin2 valid to sclk falling (si1f2-0: 011, si2f1-0: 01) t s7 30 - - ns sdin/sdin2 hold after sclk falling (si1f2-0: 011, si2f1-0: 01) t h7 30 - - ns xtal frequency 12.287 12.288 12.289 mhz xtali high time (note 4) 35 - - ns xtali low time (note 4) 35 - - ns mclk output frequency (note 4) 12.287 12.288 12.289 mhz sclk fsync lrclk sdout/sd02/sd03 sdin/sdin2 sdin/sdin2 t sclk t pd7 t fsync t lrclk t pd9 t pd8 15 0 15 0 t s6 17 16 0 17 16 0 19 18 0 19 18 0 t h6 t h7 t s7 figure 5. independent timing configuration
8 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator eeprom timing characteristics note 4. (t a = 0 to 70 c, pcivdd = cvdd = cryvdd = 3.3 v; vdd5ref = 5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v; pci clock frequency = 33 mhz; unless otherwise noted) notes: 16. rise time on eedat is determined by the capacitance on the eedat line with all connected gates and the required external pull-up resistor. parameter symbol min max units eeclk low to eedat data out valid t aa 07.0 m s start condition hold time t hd:sta 5.0 - m s eeclk low t leeclk 10 - m s eeclk high t heeclk 10 - m s start condition setup time (for a repeated start condition) t su:sta 5.0 - m s eedat in hold time t hd:dat 0- m s eedat in setup time t su:dat 250 - ns eedat/eeclk rise time (note 16) t r -1 m s eedat/eeclk fall time t f -300ns stop condition setup time t su:sto 5.0 - m s eedat out hold time t dh 0- m s eeclk eedat (in) eedat (out) t f t r t su:sta t hd:sta t hd:dat t su:dat t su:sto t aa t dh t heeclk t leeclk eedat (out) figure 6. eeprom timing
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 9 cs4622/24 crystalclear? soundfusion? pci audio accelerator overview the cs4622/24 is a high performance audio accel- erator dsp for the pci bus. this device, combined with application and driver software, provides a complete system solution for cost effective acceler- ation of windows directsound, direct-sound3d, directinput, midi playback via wavetable syn- thesis with reverberation and chorus effects pro- cessing, and more. the cs4622/24 is compatible with the cs4610c with the following added fea- tures: ? primary ac 97 interface now 2.0 compatible ? 2 nd ac 97 interface (also 2.0 compliant) ? crystalclear legacy support ? pc/pci legacy support ? ddma legacy support ? pci power management event support ? zv port asynchronous serial port ? 2nd asynchronous serial port ? 9 extended gpio pins for modem support ? consumer digital (s/pdif) input and output the cs4622 is a high-performance, full-featured version of the soundfusion audio accelerator. the CS4624 is a reduced-cost version of the cs4622. the CS4624 has a lower maximum clock speed and does not support ac-3. please refer to the oem software reference manual for more details. there are three main functional blocks within the cs4622/24: the stream processor, the pci inter- face, and the dma engine. a block diagram of the cs4622/24 device is shown in figure 7. the stream processor (sp) is a high speed custom digital signal processor (dsp) core specifically designed for audio signal processing. this ex- tremely powerful dsp core is capable of running complex algorithms such as dolby digital ac-3 audio decoding for applications such as dvd mov- ie playback or gaming. the stream processor is ca- pable of running a number of different signal processing algorithms simultaneously. this high concurrency capability is valuable for applications such as immersive 3d games, which may play a number of directsound streams, a number of directsound3d streams, and a midi music se- quence simultaneously. separate ram memories are included on-chip for the sp program code (program ram), param- eter data (parameter ram), and audio sample data (sample ram). two rom memories store 96-stream dma controller with hardware scatter/gather mpu-401 midi interface pci interface joystick interface pc/pci & ccls legacy ac '97 2.0 interface ac '97 2.0 interface s/pdif in s/pdif out zv port async. modem interface program rom parameter ram slimd sp core sample ram program ram coefficient rom figure 7. cs4622/24 block diagram
10 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator coefficients for sample rate conversion and audio decompression algorithms (coefficient rom) and common algorithm code (program rom). the ram-based dsp architecture of the cs4622/24 ensures maximum system flexibility. the software function/feature mix can be adapted to meet the requirements of a variety of different applications, such as directx? games, dvd mov- ie playback, or dos applications. this ram-based architecture also provides a means for future sys- tem upgrades, allowing the addition of new or up- graded functionality through software updates. the cs4622/24 provides an extremely efficient bus mastering interface to the pci bus. the pci inter- face function allows economical burst mode trans- fers of audio data between host system memory buffers and the cs4622/24 device. program code and parameter data are also transferred to the cs4622/24 over the pci interface. the dma engine provides dedicated hardware to manage transfer of up to 96 concurrent audio/data streams to and from host memory buffers. the dma engine provides hardware scatter-gather support, allowing simple buffer allocation and management. this implementation improves sys- tem efficiency by minimizing the number of host interrupts. the cs4622/24 supports a variety of audio i/o configurations including a single cs4297 crystal- clear ac 97 codec or dual cs4297 codecs where the second codec is used as a modem analog front end or resides in a portables docking station. the systems flexibility is further enhanced by the in- clusion of a bi-directional serial midi port, a joy- stick port, a hardware volume control interface, a zv port interface, and a serial data port which al- lows connection of an optional external eeprom device. stream processor dsp core the cs4622/24 stream processor (sp) is a custom dsp core design which is optimized for processing and synthesizing digital audio data streams. the sp features a somewhat long instruction multiple data (slimd) modified dual harvard architecture. the device uses a 40-bit instruction word and oper- ates on 32-bit data words. the sp includes two multiply-accumulate (mac) blocks and one 16- bit arithmetic and logic unit (alu). the sp core is conservatively rated at 300 million instructions per second (300 mips) when running at a 100 mhz internal clock speed (CS4624 runs at 85 mhz). the mac units perform dual 20-bit by 16-bit multiplies and have 40-bit accumulators, providing higher quality than typical 16-bit dsp architectures. a programmable phase locked loop (pll) circuit generates the high frequency internal sp clock from a lower frequency input clock. the input to the pll may be from a crystal oscillator circuit or the serial port clock abitclk/sclk. clock con- trol circuitry allows gating of clocks to various in- ternal functional blocks to conserve power during power conservation modes, as well as during nor- mal modes of operation when no tasks are being executed. legacy support legacy games are supported by crystalclear leg- acy support (ccls), ddma, or by the pc/pci in- terface. in both motherboard and add-in card designs, ccls and ddma provide support for legacy games by providing a hardware interface that sup- ports a sound blaster pro compatible interface, as well as support for fm, mpu-401, and joystick in- terfaces. these hardware interfaces provide pci- only games compatibility for real-mode dos and windows dos-box support. for motherboard designs, pc/pci can be used by connecting the pcgnt# and pcreq# pins to the
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 11 cs4622/24 crystalclear? soundfusion? pci audio accelerator appropriate pins on the south bridge motherboard chip. the pc/pci interface is compliant with in- tels pc/pci spec. (version 1.2). the bios must enable the pc/pci mechanism at boot time on both the cs4622/24 and the south bridge. system architectures a typical system diagram depicting connection of the cs4622/24 to the crystalclear cs4297 ac 97 codec is given in figure 8. all analog audio inputs and outputs are connected to the cs4297. audio data is passed between the cs4297 and the cs4622/24 over the serial ac-link. the cs4622/24 provides a hardware interface for con- nection of a joystick and midi devices. a second diagram (figure 9) depicts the cs4622/24 using both ac 97 codec interfaces in a portable design. the primary ac 97 interface is connected to a cs4297 in the portable and is used for all audio i/o inside and connected to the porta- ble. the second ac 97 interface is sent across to the docking station which contains a second cs4297, used when the portable is in the docking station. software can disable the audio i/o paths on the portable that are superseded by docking station i/o and enable the paths needed in the docking sta- tion. note that both interfaces are needed in sys- tems where the cd-rom analog input is in the portable and the line in/out jacks on the docking stations are used. using the ac 97 digital link across the dock maintains the absolute highest au- dio quality along with a standard well-defined non- proprietary interface that will last through many system generations. a third diagram (figure 10) depicts the cs4622/24 using both ac 97 codec interfaces in a modem de- sign. the primary ac 97 interface is connected to a cs4297 and is used for all traditional audio i/o such as mic in, line in, and line out. the second ac 97 interface is connected to a second cs4297 and is used as the analog front end (afe) for the modem. the second cs4297 analog interface is connected to the daa analog. the daa digital control is accomplished using the egpio pins on the cs4622/24. the egpio supports the pci pow- er management event system wake-up feature al- lowing a powered-down system to be powered up by an incoming call on the modem. host interface the cs4622/24 host interface is comprised of two separate interface blocks which are memory mapped into host address space. the interface blocks can be located anywhere in the host 32-bit physical address space. the interface block loca- tions are defined by the addresses programmed into the two base address registers in the pci config- uration space. these base addresses are normally host memory north bridge cpu south bridge cs4297 pci bus pc/pci (if used) audio out audio in figure 8. ac 97 codec interface cs4622/24 accelerator
12 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator host memory north bridge cpu south bridge cs4297 pci bus pc/pci (if used) audio out audio in cs4622/24 audio accelerator card bus interface zv port cs4297 2nd ac '97 port bridge audio out audio in secondary pci bus portable docking station figure 9. portable docking station scenario host memory north bridge cpu south bridge cs4297 pci bus pc/pci (if used) audio out audio in cs4622/24 audio accelerator card bus interface zv port cs4297 2nd ac '97 port egpio[8:0] daa telephone line figure 10. modem scenario
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 13 cs4622/24 crystalclear? soundfusion? pci audio accelerator set up by the systems plug and play bios. the first interface block (located by base address 0) is a 4 kbyte register block containing general purpose configuration, control, and status registers for the device. the second interface block (located by base address 1) is a 1 mbyte block which maps all of the internal ram memories (sp program ram, parameter ram, and sample ram) into host memory space. this allows the host to directly peek and poke ram locations on the device. the relationship between the base address registers in the cs4622/24 pci configuration space and the host memory map is depicted in figure 11. the bus mastering pci bus interface complies with the pci local bus specification (version 2.1). pci bus transactions as a target of a pci bus transaction, the cs4622/24 supports the memory read (from internal registers or memory), memory write (to internal registers or memory), configuration read (from cs4622/24 configuration registers), configuration write (to cs4622/24 configuration registers), memory read multiple (aliased to memory read), memory read line (aliased to memory read), and the memory write and invalidate (aliased to memory write) transfer cycles. the i/o read, i/o write, interrupt acknowledge, special cycles, and dual address cycle transactions are not supported. as bus master, the cs4622/24 generates the mem- ory read multiple and memory write transactions. the memory read, configuration read, configu- ration write, memory read line, memory write and invalidate, i/o read, i/o write, interrupt ac- knowledge, special cycles, and dual address cy- cle transactions are not generated. the pci bus transactions supported by the cs4622/24 device are summarized in table 1. note that no target abort conditions are signalled by the device. byte, word, and doubleword transfers are supported for configuration space accesses. only doubleword transfers are supported for register or memory area accesses. bursting is not supported for host-initiated transfers to/from the cs4622/24 internal register space, ram memory space, or pci configuration space (disconnect after first phase of transaction is completed). configuration space the content and format of the pci configuration space is given in table 2. 00h device id / vendor id status / command class code / revision base address register 0 base address register 1 misc. control direct i/o registers (memory mapped, 4 kbyte) direct memory interface (memory mapped, 1 mbyte) device pci config. space 04h 08h 0ch 10h 14h figure 11. host interface base address registers
14 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator initiator target type pci dir host registers (ba0) mem write in host registers (ba0) mem read out host memories (ba1) mem write in host memories (ba1) mem read out host config space 1 config write in host config space 1 config read out dma host system mem write out dma host system mem read in table 1. pci interface transaction summary byte 3byte 2byte 1byte 0offset device id: r/o, 6003h vendor id: r/o, 1013h 00h status register, bits 15-0: bit 15 detected parity error: error bit bit 14 signalled serr: error bit bit 13 received master abort: error bit bit 12 received target abort: error bit bit 11 signalled target abort: error bit bit 10-9 devsel timing: r/o, 01b (medium) bit 8 data parity error detected: error bit bit 7 fast back to back capable: r/o 0 bit 6 user definable features: r/o 0 bit 5 66mhz bus: r/o 0 bit 4 new capabilities: r/o 1 bit 3-0reserved: r/o 0000 reset status state: 0210h write of 1 to any error bit position clears it. command register, bits 15-0: bit 15-10: reserved, r/o 0 bit 9 fast b2b enable: r/o 0 bit 8 serr enable: r/w, default 0 bit 7 wait control: r/o 0 bit 6 parity error response: r/w, default 0 bit 5 vga palette snoop: r/o 0 bit 4 mwi enable: r/o 0 bit 3 special cycles: r/o 0 bit 2 bus master enable: r/w, default 0 bit 1 memory space enable: r/w, default 0 bit 0 io space enable: r/o 0 04h class code: r/o 040100h class 04h (multimedia device), sub-class 01h (audio), interface 00h revision id: r/o 01h 08h bist: r/o 0 header type: bit 7: r/o 0 bit 6-0: r/o 0 (type 0) latency timer: bit 7-3: r/w,default 0 bit 2-0: r/o 0 cache line size: r/o 0 0ch base address register 0 device control register space, memory mapped. 4 kbyte size bit 31-12: r/w, default 0. compare address for register space accesses bit 11 - 4: r/o 0, specifies 4 kbyte size bit 3: r/o 0, not prefetchable (cacheable) bit 2-1: r/o 00, location type - anywhere in 32 bit address space bit 0: r/o 0, memory space indicator 10h table 2. pci configuration space
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 15 cs4622/24 crystalclear? soundfusion? pci audio accelerator base address register 1 device memory array mapped into host system memory space, 1 mbyte size bit 31-20: r/w, default 0. compare address for memory array accesses bit 19 - 4: r/o 0, specifies 1 mbyte size bit 3: r/o 0, not prefetchable (cacheable) bit 2-1: r/o 00, location type - anywhere in 32 bit address space bit 0: r/o 0, memory space indicator 14h base address register 2: r/o 00000000h, unused 18h base address register 3: r/o 00000000h, unused 1ch base address register 4: r/o 00000000h, unused 20h base address register 5: r/o 00000000h, unused 24h cardbus cis pointer: r/o 00000000h, unused 28h subsystem id r/o 0000h if extee not present, otherwise r/w, loaded from eeprom subsystem vendor id r/o 0000h if extee not present, otherwise r/w, loaded from eeprom 2ch expansion rom base address: r/o 00000000h, unused 30h reserved: r/o 00000000h 34h reserved: r/o 00000000h 38h max_lat: r/o 18h 24 x 0.25us = 6 us min_gnt: r/o 04h 4 x 0.25us = 1us interrupt pin: r/o 01h, inta used interrupt line: r/w, default 0 3ch pmc bit 15: pme# from d3cold: r/o 0 bit 14: pme# from d3hot: r/o 1 bit 13: pme# from d2: r/o 1 bit 12: pme# from d1: r/o 1 bit 11: pme# from d0: r/o 1 bit 10: d2 support: r/o 1 bit 9: d1 support: r/o 1 bit 8-6: reserved: r/o 000 bit 5: device specific init: r/o 1 bit 4: auxiliary power: r/o 0 bit 3: pme# clock: r/o 1 bit 2-0: version: r/o 001 next item pointer: r/o 0h capability id: r/o 1h 40h data: r/o 0 pmcsr_bse: r/o 0 pmcsr bit 15: pme# status: r/w 0 bit 14-13: data scale: r/o 00 bit 12-9: data select: r/o 0000 bit 8: pme_en: r/w 0 bit 7-2: reserved: r/o 000000 bit 1-0: power state: r/w 00 44h byte 3byte 2byte 1byte 0offset table 2. pci configuration space (cont.)
16 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator subsystem vendor id fields the subsystem id and subsystem vendor id fields in the pci configuration space default to value 0000h unless an external eeprom device is detected or unless the host has written to the appro- priate internal register to program the values. interrupt signal the cs4622/24 pci interface includes an interrupt controller function which receives interrupt re- quests from multiple sources within the cs4622/24 device, and presents a single interrupt line (inta) to the host system. interrupt control registers in the cs4622/24 provide the host interrupt service rou- tine with the ability to identify the source of the in- terrupt and to clear the interrupt sources. in the cs4622/24, the single external interrupt is expand- ed by the use of virtual channels. each data stream which is read from or written to a modular buffer is assigned a virtual channel number. this virtual channel number is signalled by the dma subsystem anytime the associated modulo buffer pointer passes the mid-point or wraps around. vir- tual channels are also used for message passing be- tween the cs4622/24 and the host. serial port configurations a flexible serial audio interface is provided which allows connection to external analog-to-digital converters (adcs), digital-to-analog converters (dacs) or codecs (combined adc and dac functions) in several different configurations. the serial audio interface includes a primary input/out- put port with dedicated serial data pins (sdin, sd- out), two auxiliary audio output ports (sdo2, sdo3) which share pins with the joystick interface button input functions, and one auxiliary audio in- put port (sdin2). each of these digital audio input and output pins carry two channels of audio data. these two channels may comprise the left and right channels of a stereo audio signal, or two indepen- dent monaural audio signals. each digital audio channel is internally buffered through a 16 sample x 20-bit fifo. the data format for the serial digital audio ports varies depending on the configuration. the primary configuration in- cludes a cs4622/24 plus a cs4297. in addition, a dual ac 97 interface is supported where the sec- ond cs4297 is used as a modem front end or for docking station support. the cs4622/24 communicates with the cs4297 over the ac-link as specified in the intel ? audio codec 97 specification (version 1.03) with sup- port for the 2.0 extensions. a block diagram for the ac97 controller configuration is given in figure 8. the signal connections between the cs4622/24 and the ac 97 codec are indicated in figure 12. in this configuration, the ac 97 codec is the timing master for the digital audio link. the asdout output supports data transmission on all ten possible sample slots (output slots 3 - 12). the asdin input supports receiving of audio sample data on all input sample slots (input slots 3 - 12). the sdo2 and sdo3 serial outputs and the sdin2 serial input are not supported in this configuration. in the dual ac 97 system, the primary ac 97 co- dec is connected as in the single codec case; how- ever, a second cs4297 is connected to a completely separate and independent ac-link. both ac 97 codecs must use the same master clock. a block diagram depicting the dual ac97 controller configuration as a docking station is giv- en in figure 9. in this scenario, the first codec is used in the portable for traditional functions such as analog support for the portables line in, mic in, and line out jacks. the second ac link is buff- ered (along with the master clock) and sent across to the docking station to support a second cs4297 that supports the docks analog jacks. when the system gets a message that the docking station is at- tached, the software can replace the portables ana- log jack control for the docking stations jacks seemlessly. using a standard ac link for the dock- ing station support maintains the highest quality of
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 17 cs4622/24 crystalclear? soundfusion? pci audio accelerator audio over analog docking station scenarios. in ad- dition, since the ac link is a standard, the docking station can be utilized over a number of portable generations without concern for obsolescence. a block diagram depicting the dual ac97 con- troller configuration as a modem analog front end is illustrated in figure 10. in this scenario, the pri- mary ac 97 codec is used for the traditional sup- port of analog i/o. the second cs4297 is utilized as the analog front end connected to the analog daa interface. the digital daa control is sup- ported through the extended general purpose i/o (egpio) pins on the cs4622/24. the signal connections between the cs4622/24 and the dual codecs are shown in figure 13. in this configuration, both ac 97 codecs must run off the same master clock with the primary ac 97 codec being the timing master for the first ac link and for the cs4622/24. the secondary cs4297 is tim- ing master for the second ac-link. full fifo buff- ers for both links are supported. midi port in the ac 97 controller configuration, a bi-direc- tional midi interface is provided to allow connec- tion of external midi devices. the midi interface includes 16-byte fifos for the midi transmit and receive paths. joystick port in the ac 97 controller configuration, a joystick port is provided. the joystick port supports four coordinate channels and four button channels. the coordinate channels provide joystick position- al information to the host, and the button channels provide user button event information. the joystick interface is capable of operating in the traditional polled mode, but also provides a hardware ac- celerated mode of operation wherein internal counters are provided to assist the host with coordi- nate position determination. the joystick schemat- ic is illustrated in figure 14. eeprom interface the eeprom configuration interface allows the connection of an optional external eeprom de- vice to provide power-up configuration informa- tion. the external eeprom is not required for proper operation; however, in some applications power-up configuration settings other than the de- abitclk async asdout asdin arst# midiin midiout jacx, jacy, jbcx, jbcy jab1, jab2, jbb1, jbb2 joystick/ midi port bit_clk sync sdata_out sdata_in reset# 24.576 mhz cs4297 12.288 mhz 48 khz analog interface figure 12. ac 97 codec connection diagram cs4622/24
18 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator abitclk async asdout asdin arst# midiin midiout jacx, jacy, jbcx, jbcy jab1, jab2, jbb1, jbb2 joystick/ midi port bit_clk sync sdata_out sdata_in reset# 24.576 mhz cs4297 12.288 mhz 48 khz abitclk2 async2 asdout2 asdin2 arst2# bit_clk sync sdata_out sdata_in reset# second cs4297 12.288 mhz 48 khz cs4622/24 analog interface analog interface xtali xtali figure 13. dual ac 97 codec connection diagram +5 v dsp 1 nf 1 9 8 4 5 2 10 7 14 12 15 1 nf 5.6 nf 5.6 nf 2.2 k w 2.2 k w midiin midiout jab2 jbb2 jacy jbcy jbcx jacx jbb1 jab1 3 11 13 6 1 nf 1 nf 2.2 k w 2.2 k w 5.6 nf 5.6 nf 4.7 k w 4.7 k w 4.7 k w 4.7 k w 4.7 k w figure 14. joystick logic
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 19 cs4622/24 crystalclear? soundfusion? pci audio accelerator fault values may be required to support specific operating system compatibility requirements. after a hardware reset, an internal state machine in the cs4622/24 will automatically detect the pres- ence of an external eeprom device (assuming eepdis is low) and load the subsystem id and subsystem vendor id fields, along with two bytes of general configuration information, into internal registers. at power-up, the cs4622/24 will attempt to read from the external device, and will check the data received from the device for a valid signature header. if the header data is invalid, the data trans- fer is aborted. after power-up, the host can read or write from/to the eeprom device by accessing specific registers in the cs4622/24. cirrus logic provides software to read and write the eeprom. the two-wire interface for the optional external eeprom device is depicted in figure 15. during data transfers, the data line (eedat) can change state only while the clock signal (eeclk) is low. a state change of the data line while the clock sig- nal is high indicates a start or stop condition to the eeprom device. the eeprom device read access sequence is shown in the figure 16. the timing follows that of a random read sequence. the cs4622/24 first performs a dummy write operation, then generates a start condition followed by the slave device address and the byte address of zero. the cs4622/24 always begins access at byte address zero and continues access a byte at a time, using a sequential read, until all needed bytes in the eeprom are read. since only 7 bytes are needed, the smallest eeprom available will suffice. general purpose i/o pins many of the cs4622/24 signal pins are internally multiplexed to serve different functions depending on the environment in which the device is being used. several of the cs4622/24 signal pins may be used as general purpose i/o pins when not required for other specific functions in a given application. zv port serial interface the zv port interface consists of three input pins: zlrck, zsclk, and zsdata. zlrck is the left/right clock indicating which channel is currently being received. zsclk is the serial bit clock where zlrck and zsdata change on the falling edge and serial data is internally latched on the rising edge. note that the serial data starts one zsclk period after zlrck transitions. figure 17 illustrates the clocking on the zv port pins. zv port is available only in the cs4280-cq. slimd sp core eedat eeclk 4.7 k w 2-wire serial eeprom figure 15. external eeprom connection s1 0 1 0 0 0 0 0 a0 0 0 0 0 0 0 0 as 1 0 1 0 0 0 0 1 a data data p 1 a start part address start acknowledge no acknowledge stop acknowledge data eeprom write read bank address part address dsp figure 16. eeprom read sequence
20 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator consumer iec-958 digital interface (s/pdif) the cs4622/24 supports the industry standard iec-958 consumer digital interface. sometimes this standard is referred to as s/pdif, which refers to an older version of this standard. this output provides an interface, external to the pc, for storing digital audio (as in a dat or recordable cd-rom) or playing digital audio from digital speakers. figure 18 illustrates the circuit necessary for imple- mentation of the iec-958 consumer interface. an external buffer is required to drive the current needed to drive the 75 w interface. a current driver is implemented to increase the transmission range of the coaxial circuitry. figure 19 illustrates an optional fiber optic circuit. the optical circuit connects directly to the cs4622/24 and no additional current driver is needed. zlrck zsclk left channel right channel zsdata 6 54 3 210 98 7 15 14 13 12 11 10 654 32 10 9 87 15 14 13 12 11 10 figure 17. zv port clocking format +5v_pci dgnd dgnd dgnd dgnd dgnd iec_958_rx spdifi spdifo iec_958_tx .01uf j-rca-ra-pcb 1 2 0.01uf 1 2 75 1 2 90.9 1 2 29398 1 5 4 8 j-rca-ra-pcb 1 2 374 1 2 0.1uf u9 sn75179d r 2 d 3 a 8 b 7 y 5 z 6 vc c 1 gn d 4 figure 18. iec consumer interface implementation circuit
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 21 cs4622/24 crystalclear? soundfusion? pci audio accelerator egpio in addition to the gpio pins on the cs4622/24, ex- tended general purpose i/o has been added. five egpio pins are not multiplexed, egpio[8:7, 2:0]; whereas; egpio[6:3] are shared with the asyn- chronous serial port. when this second async. seri- al port is not used, all the egpio pins are available. these pins have extended functionality in that any egpio pin can be programmed to cause a power management wake-up event on the pme# signal. this feature enables an incoming call on a modem to wake-up a powered-down system without user intervention. these pins also can be programmed as: ? input or output, ? edge or level sensitive (sticky), ? active high or low input, ? cmos or open-drain output dgnd dgnd dgnd dgnd dgnd dgnd +5v_pci +5v_pci spdifo spdifi totx-173 1 2 3 4 5 6 8.2k 1k torx-173 1 2 3 4 5 6 .1uf .1uf 47uh figure 19. optional fiber optic circuit
22 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator pin description egpio[3]/asclk 103 egpio[4]/asfclk 104 egpoi[5]/asdi 105 egpio[6]/asdo 106 asdin2 107 pme# 108 inta# 109 rst# 110 pciclk 111 gnt# 112 req# 113 pcivdd[0] 114 pcignd[0] 115 ad[31] 116 ad[30] 117 ad[29] 118 ad[28] 119 ad[27] 120 pcignd[1] 121 pcivdd[1] 122 ad[26] 123 ad[25] 124 ad[24] 125 c/be[3]# 126 idsel 127 pcivdd[2] 128 test 65 jacx 66 jacy 67 jbcx 68 jbcy 69 jab1/sdo2 70 jab2/sdo3 71 jbb1/lrclk 72 jbb2/mclk 73 midiin 74 cvdd[2] 75 cgnd[2] 76 midiout 77 cvdd[3] 78 cgnd[3] 79 zlrclk 80 zsclk 81 zsdata 82 spdifi 83 spdifo 84 egpio[0] 85 egpio[1] 86 egpio[2] 87 sdin2/gpio 88 cgnd[4] 89 cvdd[4] 90 cryvdd 91 volup/xtali 92 voldn/xtalo 93 crygnd 94 vdd5ref 95 abitclk/sclk 96 asdout/sdout 97 asdin/sdin 98 async/fsync 99 arst# 100 eeclk/pcreq# 101 eedat/pcgnt# 102 38 pcignd[5] 37 ad[14] 36 ad[15] 35 c/be[1]# 34 par 33 serr# 32 perr# 31 stop# 30 pcignd[4] 29 pcivdd[4] 28 devsel# 27 cvdd[0] 26 cgnd[0] 25 trdy# 24 irdy# 23 eepdis 22 21 20 19 18 17 16 15 frame# 14 c/be[2]# 13 cgnd[1] 12 cvdd[1] 11 ad[16] 10 ad[17] 9 ad[18] 8 pcivdd[3] 7 pcignd[3] 6 ad[19] 5 ad[20] 4 ad[21] 3 ad[22] 2 ad[23] 1 pcignd[2] 64 clkrun# 63 egpio[7] 62 arst2# 61 async2 60 asdout2 59 abitclk2 58 pcivdd[7] 57 pcignd[7] 56 ad[0] 55 ad[1] 54 ad[2] 53 ad[3] 52 ad[4] 51 ad[5] 50 ad[6] 49 ad[7] 48 pcignd[6] 47 pcivdd[6] 46 c/be[0]# 45 ad[8] 44 ad[9] 43 ad[10] 42 ad[11] 41 ad[12] 40 ad[13] 39 pcivdd[5] 128-pin tqfp cs462x-cq
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 23 cs4622/24 crystalclear? soundfusion? pci audio accelerator a # sign suffix on a pin names indicates an active-low signal. pci interface ad[31:0] - address/data bus, i/o, pins 116-120, 123-125, 2-6, 9-11, 36-37, 40-45, 49-56 these pins form the multiplexed address / data bus for the pci interface. c/be[3:0]# - command type / byte enables, i/o, pins 126, 14, 35, 46 these four pins are the multiplexed command / byte enables for the pci interface. during the address phase of a transaction, these pins indicate cycle type. during the data phases of a transaction, active low byte enable information for the current data phase is indicated. these pins are inputs during slave operation and they are outputs during bus mastering operation. par - parity, i/o, pin 34 the parity pin indicates even parity across ad[31:0] and c_be[3:0] for both address and data phases. the signal is delayed one pci clock from either the address or data phase for which parity is generated. frame# - cycle frame, i/o, pin 15 frame# is driven by the current pci bus master to indicate the beginning and duration of a transaction. irdy# - initiator ready, i/o, pin 24 irdy# is driven by the current pci bus master to indicate that as the initiator it is ready to transmit or receive data (complete the current data phase). trdy# - target ready, i/o, pin 25 trdy# is driven by the current pci bus target to indicate that as the target device it is ready to transmit or receive data (complete the current data phase). stop# - transition stop, i/o, pin 31 stop# is driven active by the current pci bus target to indicate a request to the master to stop the current transaction. idsel - initialize device select, input, pin 127 idsel is used as a chip select during pci configuration read and write cycles. devsel# - device select, i/o, pin 28 devsel# is driven by the pci bus target device to indicate that it has decoded the address of the current transaction as its own chip select range.
24 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator req# - master request, three-state output, pin 113 req# indicates to the system arbiter that this device is requesting access to the pci bus. this pin is high-impedance when rst# is active. gnt# - master grant, input, pin 112 gnt# is driven by the system arbiter to indicate to the device that the pci bus has been granted. perr# - parity error, i/o, pin 32 perr# is used for reporting data parity errors on the pci bus. serr# - system error, open drain output, pin 33 serr# is used for reporting address parity errors and other catastrophic system errors. inta# - host interrupt a (for sp), open drain output, pin 109 inta# is the level triggered interrupt pin dedicated to servicing internal device interrupt sources. pciclk - pci bus clock, input, pin 111 pciclk is the pci bus clock for timing all pci transactions. all pci synchronous signals are generated and sampled relative to the rising edge of this clock. rst# - pci device reset, pin 110 rst# is the pci bus master reset. vdd5ref: clean 5 v power supply, pin 95 vdd5ref is the power connection pin for the 5 v pci pseudo supply for the pci bus drivers. the internal core logic runs on 3.3 volts. this pin enables the pci interface to support and be tolerant of 5 volt signals. must be connected to +5 volts. pcivdd[7:0] - pci bus driver power supply, pins 58, 47, 39, 29, 8, 128, 122, 114 pcivdd pins are the pci driver power supply pins. these pins must have a nominal +3.3 volts. pcignd[7:0] - pci bus driver ground pins, pins 57, 48, 38, 30, 7, 1, 121, 115 pcignd pins are the pci driver ground reference pins. pme# - pci power management event, open drain output, pin 108 pme# signals a power management event. this signal can go low because of an ac 97 2.0 codec, an event on a egpio[8:0] bit, or host software.
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 25 cs4622/24 crystalclear? soundfusion? pci audio accelerator external interface pins test - test mode strap, input, pin 65 this pin is sampled at reset for test mode entry. if it is high at reset, test mode is enabled. this pin must be pulled to ground for normal operation. eedat/pcgnt# - eeprom data line / pc/pci grant, i/o, pin 102 for expansion card designs, this is the data line for external serial eeprom containing device configuration data. when used with an external eeprom (eepdis must be low), a 4.7 k w pullup resistor is required. in motherboard designs using pc/pci, this pin is the pc/pci serialized grant input. in designs with neither of the above requirements, this pin can be used as a general purpose input or open drain output (gpio2). eeclk/pcreq# - eeprom clock line / pc/pci request, output, pin 101 for expansion card designs, this is the clock line for external serial eeprom containing device configuration data (eepdis must be low). in motherboard designs using pc/pci, this pin is the pc/pci serialized request output. in designs with neither of the above requirements, this pin can be used as a general purpose output pin (gpout). eepdis - eeprom disable, input, pin 23 this strapping pin, when tied high, disables the eeprom interface. when low, the cs4622/24 checks at power-up for an external eeprom on the eeclk and eedat pins. sdin2/gpio - serial data input 2 / general purpose i/o pin, i/o, pin 88 this dual function pin defaults as a general purpose i/o pin. in non-ac 97 system configurations, this pin can function as a second stereo digital data input pin if enabled. volup/xtali - volume-up button / crystal in, input, pin 92 this dual function pin is either the volume-up button control input or the crystal oscillator input pin, depending on system configuration. this pin may also be used as a general purpose input if its primary function is not needed. voldn/xtalo - volume-down button / crystal output, i/o, pin 93 this dual function pin is either the volume-down button control input or the crystal oscillator output pin, depending on system configuration. this pin may also be used as a general purpose input if its primary function is not needed.
26 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator clock / miscellaneous clkrun# - optional system clock control, pin 64 clkrun# is an optional pci signal defined for mobile operations. this is an open drain output signalling the system that the pci clock is required. this signal pin is not available on the add-in card connector. cryvdd - crystal & pll power supply, pin 91 power pin for crystal oscillator and internal phase locked loop. this pin must be connected to a nominal +3.3 volts. crygnd - crystal & pll ground supply, pin 94 ground pin for crystal oscillator and internal phase locked loop. jacx, jacy, jbcx, jbcy - joystick a and b x/y coordinates, i/o, pins 66, 67, 68, 69 these pins are the 4 axis coordinates for the joystick port. these pins may also be used as a general purpose inputs or open drain outputs if their primary function is not needed. jab1/sdo2 - joystick a button 1 / serial data output 2, i/o, pin 70 this dual function pin defaults as jab1 (button 1 input for joystick a). in non-ac 97 system configurations, this pin can function as a second stereo digital data output pin if enabled. this pin can also be a general purpose polled input if a second data output stream is not required. jab2/sdo3 - joystick a button 2 / serial data output 3, i/o, pin 71 this dual function pin defaults as jab2 (button 2 input for joystick a). in non-ac 97 system configurations, this pin can function as a third stereo digital data output pin if enabled. this pin can also be a general purpose polled input if a third data output stream is not required. jbb1/lrclk - joystick b button 1 / l/r framing clock, i/o, pin 72 this dual function pin defaults as jbb1 (button 1 input for joystick b). in non-ac 97 system configurations, this pin can function as a left/right framing clock output pin for sdo2 and sdo3. this pin can also be used as a general purpose polled input if alternate data output streams are not required. jbb2/mclk - joystick b button 2 / master clock, i/o, pin 73 this dual function pin defaults as jbb2 (button 2 input for joystick b). in non-ac 97 system configurations, this pin can function as a master (256x sample rate) output clock if enabled. this pin can also be used as a general purpose polled input if alternate data output streams are not required. midiin - midi data input, pin 74 this is the serial input pin for the internal midi port.
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 27 cs4622/24 crystalclear? soundfusion? pci audio accelerator midiout - midi data output, pin 77 this is the serial output pin for the internal midi port. cvdd[4:0] - core power supply, pins 90, 78, 75, 12, 27 core / stream processor power pins. these pins must be connected to a nominal +3.3 volts. cgnd[4:0] - core ground supply, pins 89, 79, 76, 13, 26 core / stream processor ground reference pins. serial codec interface abitclk/sclk - primary ac 97 bit clock / serial audio data clock, i/o, pin 96 master timing clock for serial audio data. in ac 97 configurations, this pin is an input which drives the timing for the ac 97 interface, along with providing the source clock for the cs4622/24. in external dac configurations, it an output, providing the serial bit clock. async/fsync - primary ac 97 frame sync / serial audio frame sync, i/o, pin 99 framing clock for serial audio data. in ac 97 configurations, this pin is an output which indicates the framing for the ac 97 link. in external dac configurations, this pin is an fsync output, providing the left/right framing clock. asdout/sdout - primary ac 97 data out / serial audio data out, output, pin 97 ac 97 serial data out / serial audio output data. arst# - primary ac 97 reset, output, pin 100 ac 97 link reset pin. this pin also functions as a general purpose reset output in non-ac 97 configurations and will follow rst# to ground, but must be forced high by software. asdin/sdin - primary ac 97 data in / serial audio data in, input, pin 98 serial audio input data. asdin2 - second ac 97 data in, pin 107 ac 97 (2.0) serial audio input data for the second ac 97 codec. the other ac link pins are either shared with the first ac 97 interface or connected to the second complete ac 97 interface listed below. abitclk2 - second ac 97 link bit clock, input, pin 59 master timing clock for the second ac 97 serial link. async2 - second ac 97 link frame sync, output, pin 61 framing clock for second ac 97 link serial audio data. this pin is an output which indicates the framing for the second ac 97 link.
28 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator asdout2 - second ac 97 link data out, output, pin 60 ac 97 serial data out / serial audio output data. arst2# - second ac 97 link reset, output, pin 62 second ac 97 link reset pin. this pin also functions as a general purpose reset output in non- ac 97 configurations and will follow rst# pin 82 to ground, but must be forced high by software. zv port serial interface zsclk - zv port serial clock, input, pin 81 zv port serial bit clock. zlrclk - zv port left/right clock, input, pin 80 zv port left/right channel delineation. zsdata - zv port serial data in, input, pin 82 zv port serial data input pin. consumer digital audio i/o (s/pdif) spdifo - consumer digital audio out, output, pin 84 this cmos pin outputs serial data that conforms to the iec-958 consumer format. the data is bi-phase mark encoded and requires external drivers. spdifi - consumer digital audio in, input, pin 83 this pin receives asynchronous serial data that conforms to the iec-958 consumer format. the data should be bi-phase mark encoded. asynchronous serial interface and enhanced general purpose i/o asclk/egpio[3] - async. serial port clock / enhanced gen. purpose i/o, i/o, pin 103 serial clock that controls the asynchronous serial interface. as asclk, this pin can be either an async. input bit clock or, when the ac 97 interface is enabled, can be an output programmed for a frequency of abitclk/4. when not used as an async. port bit clock, this pin is enhanced general purpose i/o bit 3 (see egpio[8:7, 2:0] for more details.) asfclk/egpio[4] - async. serial frame clock / enhanced gen. purpose i/o, i/o, pin 104 serial frame signal that delineates left from right data. as asflck, this pin can be either an input l/r framing clock that must be synchronous to asclk, or when the ac 97 interface is enabled, an output fixed at asclk/64. when not used as an async. port framing signal, this pin is enhanced general purpose i/o bit 4 (see egpio[8:7, 2:0] for more details.)
ds293pp2 cirrus logic preliminary product bulletin june 30, 4:24 pm 29 cs4622/24 crystalclear? soundfusion? pci audio accelerator asdi/egpio[5] - async. serial port data in / enhanced gen. purpose i/o, i/o, pin 105 when used as asdi, stereo data is clocked into the cs4622/24 with asclk with asfclk delineating left from right. otherwise, this pin is enhanced general purpose i/o bit 5 (see egpio[8:7, 2:0] for more details.) asdo/egpio[6] - async. serial port data out / enhanced gen. purpose i/o, i/o, pin 106 when used as asdo, stereo data is clocked out of the cs4622/24 using asclk with asfclk delineating left from right. otherwise, this pin is enhanced general purpose i/o bit 6 (see egpio[8:7, 2:0] for more details.) egpio[7, 2:0] - extended general purpose i/o bits, i/o, pins 63, 87, 86, 85 these bits along with bits egpio[6:3] have extended programmability and can be used for any application such as modem daa control. programmability features include: direction, polarity, level/edge sensitive, and the ability to set pme# active for a power management wake-up event.
30 cirrus logic preliminary product bulletin june 30, 4:24 pm ds293pp2 cs4622/24 crystalclear? soundfusion? pci audio accelerator package outline q package 128-pin tqfp e1 e d1 d 1 e l b a1 a inches millimeters dim min nom max min nom max a 0.000 0.063 0.000 1.600 a1 0.002 0.006 0.050 0.150 b 0.007 0.011 0.170 0.270 d 0.626 0.634 15.900 14.000 16.100 d1 0.547 0.555 13.900 14.100 e 0.862 0.870 21.900 22.100 e1 0.783 0.791 19.900 20.000 20.100 e 0.016 0.024 0.400 0.500 0.600 0.000 7.000 0.000 7.000 l 0.018 0.030 0.450 0.750
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